The present invention is directed to printed circuit boards or substrates, and, more particularly, to a via within a printed circuit board or substrate filled with solder.
Electronic components are typically assembled into complex circuits by mounting them on multilayer devices, such as printed circuit boards (PCBs) and/or multilayer substrates. Multiple layers that serve to electrically connect one or more electronic components to other electronic components attached to a different layer or the layers themselves, must be electrically connected to each other at selected points, requiring use of what is commonly known as a via, which is formed as a cylindrical hole in one or more layers of the substrate or printed circuit board. To electrically interconnect various electronic components and/or layers to one another, a wall of the via or hole is plated, by a plating process, with a conducting material, such as copper, aluminum, gold, or silver and subsequently filled with a material, such as via plug resin, solder resist, or solder materials.
Unfortunately, the conventional plating and via filling processes are time consuming, costly, and can have significant defects. For example, the via plating process can create cavities or “voids” between a conductive layer and non-conducting layers, which can become sites for chemical contamination and corrosion, thus interfering with the conductivity of the layers. Other defects that may occur during manufacturing include improper via filling, high via stress, and plated via cracking, which may potentially cause failure of the multilayer device, and create long term reliability issues.
It is therefore desirable to provide a method for manufacturing a semiconductor device with a solder filled via in a manner that is not susceptible to the plating and other possible defects that may occur using conventional via filling processes.